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  <comment>SystemVerilog source code</comment>
  <comment xml:lang="bg">Изходен код — SystemVerilog</comment>
  <comment xml:lang="ca">codi font en SystemVerilog</comment>
  <comment xml:lang="cs">zdrojový kód SystemVerilog</comment>
  <comment xml:lang="da">SystemVerilog-kildekode</comment>
  <comment xml:lang="de">SystemVerilog-Quelltext</comment>
  <comment xml:lang="el">Πηγαίος κώδικας SystemVerilog</comment>
  <comment xml:lang="en_GB">SystemVerilog source code</comment>
  <comment xml:lang="es">código fuente en SystemVerilog</comment>
  <comment xml:lang="eu">SystemVerilog iturburu-kodea</comment>
  <comment xml:lang="fi">SystemVerilog-lähdekoodi</comment>
  <comment xml:lang="fr">code source </comment>
  <comment xml:lang="gl">código fonte en SystemVerilog</comment>
  <comment xml:lang="he">קוד מקור של SystemVerilog</comment>
  <comment xml:lang="hr">SystemVerilog izvorni kod</comment>
  <comment xml:lang="hu">SystemVerilog-forráskód</comment>
  <comment xml:lang="ia">Codice-fonte SystemVerilog</comment>
  <comment xml:lang="id">Kode sumber SystemVerilog</comment>
  <comment xml:lang="it">Codice sorgente </comment>
  <comment xml:lang="ja">SystemVerilog ソースコード</comment>
  <comment xml:lang="kk">SystemVerilog бастапқы коды</comment>
  <comment xml:lang="ko">SystemVerilog 소스 코드</comment>
  <comment xml:lang="lv">SystemVerilog pirmkods</comment>
  <comment xml:lang="nl">SystemVerilog broncode</comment>
  <comment xml:lang="pl">Kod źródłowy SystemVerilog</comment>
  <comment xml:lang="pt_BR">Código-fonte de SystemVerilog</comment>
  <comment xml:lang="ru">исходный код SystemVerilog</comment>
  <comment xml:lang="sk">Zdrojový kód SystemVerilog</comment>
  <comment xml:lang="sl">Datoteka izvorne kode SystemVerilog</comment>
  <comment xml:lang="sr">изворни код Система Верилога</comment>
  <comment xml:lang="sv">SystemVerilog-källkod</comment>
  <comment xml:lang="tr">SystemVerilog kaynak kodu</comment>
  <comment xml:lang="uk">вихідний файл мовою SystemVerilog</comment>
  <comment xml:lang="zh_CN">SystemVerilog 源代码</comment>
  <comment xml:lang="zh_TW">SystemVerilog 原始碼</comment>
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